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Triple-Output Power-Management IC for
Microprocessor-Based Systems
=
R C = L OUT
=
C COMPHF _ = ESR OUT , but not less than 33 pF
? V OUT ( MAX ) ? ? 1 ? ? 1 ?
I OUT ( MAX ) ? ? ? R CS ? ? ? 2 × π × f ?
C COMP 1 / 3 = ? ? ? ? g m
Compensation and Stability
Compensate each regulator by placing a resistor and a
capacitor in series, from COMP_ to GND and connect a
33pF capacitor from COMP_ to GND for improved
noise immunity (Figure 1). The capacitor integrates the
current from the transconductance amplifier, averaging
output-voltage ripple. This sets the device speed for
transient responses and allows the use of small ceram-
ic output capacitors. The resistor sets the proportional
gain of the output error voltage by a factor g m ? R C .
Increasing this resistor also increases the sensitivity of
the control loop to the output-voltage ripple.
This resistor and capacitor set a compensation zero
that defines the system ’ s transient response. The load
pole is a dynamic pole, shifting frequency with changes
in load. As the load decreases, the pole frequency
shifts lower. System stability requires that the compen-
sation zero must be placed properly to ensure ade-
quate phase margin (at least 30 ° ). The following is a
design procedure for the compensation network:
1) Select an appropriate converter bandwidth (f C ) to
stabilize the system while maximizing transient
response. This bandwidth should not exceed 1/5 of
the switching frequency. Use 100kHz as a reason-
able starting point.
2) Calculate the compensation capacitor, COMP_,
based on this bandwidth. Calculate COMP1 and
COMP3 with the following equation:
?
where RCS is the regulator ’ s current-sense transre-
sistance and gm is the regulators error amplifier
transconductance. Calculate COMP2 with the fol-
lowing equation:
the output capacitor, C OUT (see the Output Capacitor
Selection section). Calculate the compensation resis-
tance (R C ) value to cancel out the dominant pole creat-
ed by the output load and the output capacitance:
1 1
2 × π × R L × C OUT 2 × π × RC × C COMP_
Solving for R C gives:
R × C
C COMP _
To find C COMPHF_ , calculate the high-frequency com-
pensation pole to cancel the zero created by the output
capacitor ’ s equivalent series resistance (ESR):
1 1
2 × π × R ESR × C OUT 2 × π × R C × C COMPHF_
Solving for C COMPHF_ gives:
R × C
R C
If low-ESR ceramic capacitors are used, the C COMPHF_
equation can yield a very small capacitance value. In
such cases, do not use less than 33pF to maintain
noise immunity.
Inductor Selection
A 4.7μH inductor with a saturation current of at least
1.5A is recommended for most applications. For best
efficiency, use an inductor with low ESR. See Table 1
for recommended inductors and manufacturers. For
most designs, a reasonable inductor value (L IDEAL ) can
be derived from the following equation:
? V OUT ( MAX ) ? ? 1 ? ? 1 ? ? R 5 ?
? ? ? 2 × π × f ? ? ? ? g m × R 4 + R 5 ? ?
C COMP 2 = ? ? ?
? I OUT ( MAX ) ? ? R CS ?
L IDEAL =
V OUT ( V IN ? V OUT )
V IN × LIR × I OUT ( MAX ) × f OSC
R L =
I LMAX = ? 1 +
? I OUT ( MAX )
where R CS is REG2 ’ s current-sense transresistance
and g m is REG2 ’ s error-amplifier transconductance.
Calculate the equivalent load impedance, R L , by:
V OUT ( MIN )
I OUT ( MAX )
where V OUT(MIN) equals the minimum output voltage.
I OUT(MAX) equals the maximum load current. Choose
where LIR is the inductor current ripple as a percent-
age of the load current.
LIR should be kept between 20% and 40% of the maxi-
mum load current for best performance and stability.
The maximum inductor current is:
? LIR ?
? 2 ?
______________________________________________________________________________________
15
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